high speed digital test forum 2025 -55体育

global digitalization, big data and ai: drivers, trends, opportunities and new design challenges

• martin stumpf, segment manager high-speed digital test, rohde & schwarz
• kristof mommen, general manager & vice-president of business development, granite river labs emea

digitalization is everywhere and with this the demand for increasing processing power and data rates. this applies for data centers and ai, but also for many other areas like autonomous driving, industry automation, aerospace & defense and wireless communication. we will explore major trends and the evolution of the related technologies and will discuss the impact on high-speed designs and their power distribution networks as well as the increasing challenges in signal integrity and power integrity.

power designs for high-speed socs with multi-phase buck converters

• tim paasch-colberg, product manager, rohde & schwarz
• korbinian schmidt-sommerfeld, application engineer, rohde & schwarz
• jürgen neuhäusler, senior applications engineer, texas instruments

the increasing complexity of high-speed system-on-chips (socs) and fpgas poses significant challenges for power design. as functionality and processing power rise, so do the demands on power management. this necessitates the use of multiple power rails and innovative power supply architectures, such as multiphase buck converters. while these converters offer advantages, they also introduce new design and validation complexities, particularly for high-current power rails. rohde & schwarz oscilloscopes, equipped with advanced analysis capabilities, can effectively support the testing and analysis of these intricate power designs, allowing engineers to precisely measure and validate the performance of multiphase buck converters.

usb3.2 interfaces: signal integrity analysis & compliance testing

• johannes ganzert, senior application engineer, oscilloscopes, rohde & schwarz
• pascal berten, laboratory director, granite river labs emea

this class is aimed at engineers who test & debug usb interfaces. in particular, we will discuss the details of usb 3.2 gen 1 and gen 2 electrical compliance testing. during the session, you will gain insight into the requirements and test setups for transmitter (tx) and receiver (rx) tests, covering topics such as spread spectrum clocking, jitter and eye diagram analysis, pre-shoot/de-emphasis, and more. we will examine potential sources of failure if the compliance check fails and discuss the use of tools to help identify the root causes of compliance failures.

automotive ethernet: the key to unlocking zonal architecture

• jithu abraham, product manager, oscilloscopes, rohde & schwarz
• rainer eckelt, global director automotive, granite river labs

as the automotive industry looks to developing the future software defined vehicle (sdv), increased levels of autonomous driving requiring more sensors and increased connectivity brings forth challenges of transporting and processing a huge amount of data in the vehicle. to do this in an efficient way, it is necessary to reduce in-vehicle network complexity, power consumption and weight, leading to a change from domain-orientated network architecture to zonal architecture. this session focuses on such trends and significant development in in-vehicle networks such as 10base-t1s and multigig speeds and how to test these new networks effectively.

ddr memory interfaces: signal integrity analysis & compliance testing

• guido schulze, product manager, oscilloscopes, rohde & schwarz
• johannes ganzert, senior application engineer, oscilloscopes, rohde & schwarz

the integration of ddr and lpddr devices in systems often causes challenges for signal and power integrity. we will provide an overview about ddr technologies and key parameters for testing. learn about effective tools for debugging and characterization as well as automated test solutions for conformance verification. another challenge for ddr testing is the connectivity via interposers. see on a practical example how to de-embed the effects of the interposer correctly and utilize the power of debugging tools such as zone trigger or read/ write decoding for eye diagram analysis.

mipi d-phy: signal integrity analysis & compliance testing

• guido schulze, product manager, oscilloscopes, rohde & schwarz
• alessandro cappelletti, senior application engineer - oscilloscopes, rohde & schwarz
• pascal berten, laboratory director, granite river labs emea

the mipi d-phy interface was originally developed to enable high-speed data transmission between cameras and displays in mobile phones. today, it has gained widespread adoption in automotive, consumer and industrial applications. learn about the mipi d-phy interface architecture and key parameters of the physical layer. we will provide an overview of the specified conformance tests, highlight challenges unique to these tests and discuss recommended measurement setups. in case of failures, effective tools such as the advanced eye diagram analysis and jitter decomposition can be used to troubleshoot efficiently.

testing dp 1.4a sources with oscilloscopes - phy layer compliance

• alessandro cappelletti, senior application engineer - oscilloscopes, rohde & schwarz

we are going to explore displayport 1.4a physical layer compliance testing for high-speed digital design. after a technology overview and compliance test requirements, we demonstrate how the rtp oscilloscope can streamline verification. learn how to debug with signal integrity tools like eye diagram analysis, and pinpoint issues by using jitter and noise decomposition utilities. practical examples illustrate effective troubleshooting for reliable compliance.

accurate test fixture characterization and de-embedding for correct measurements with oscilloscopes and vnas in high-speed digital applications

• jörn pfeifer, application engineer vector network analysis, rohde & schwarz
• pascal berten, laboratory director, granite river labs emea

modern oscilloscopes and vnas can mathematically remove, i.e. de-embed the lead-ins to the dut (e.g. test fixtures, probes, etc.) and measure the correct dut performance at the defined reference planes. this is done by modelling the lead-in via a touchstone file. we will discuss the various use cases, the method of impedance corrected de-embedding to generate accurate lead-in models with a vna and share best practice experience.

characterizing the high-speed transmission channel – measurement challenges and advanced test tools

• bryant hsu, product manager, rohde & schwarz

high-speed pcb/interconnect design and validation testing poses significant challenges with increasing data rates. characterizing transmission channels requires higher frequency testing and multi-port setups to effectively analyze the lane-to-lane crosstalk. this presentation shows various use cases as example. key concerns for achieving accurate and time-efficient measurements are addressed by using specialized tools such as time domain and enhanced time domain analysis, multiport s-parameter snp assistant, and r&s®znrun cable compliance test automation.